Advantages of FIBULA - SICORE 

Conventional DSP development phase


our solution with FIBULA-SICORE



Looking for a high level of abstrastion leads to a complex and costly operating mode when using conventional methods. Code rewrite is teddious and bug prone, system debugging can last long. This method leads to using bigger, more expensive, more power consumming DSP chips. It usually involves several engineers.


The FIBULA-SICORE solution is simple, smart, efficient and low cost at all levels. Only one engineer can easily handle all the project. 



Some of the numerous advantages regarding DSP in general:

Conventional method


- A conventional computing and prototyping system can cost well over 10k€

- The developement tools for the embedded DSP implementation have to be added (starting 2k€)

- Before implementing, an eval board of the DSP has to be purchased, then costly multilayer PCBs prototypes of the system board have to be designed and manufactured.

- Weeks to months of engineering just for porting and debugging the code...

Low cost investment, only one tool chain, only one engineer on the project. Just simple!

Principle validated = product ready (no recoding, no porting, engineer once only!)

Fast time to market

Use of costly high performance scopes for system debugging (still impossible to visualize signals inside the DSP / FPGA). Probes placement is challenging and often impossible with fine pitch components and BGA packages.

Enables signals visualization everywhere, without using a traditional scope, even where no physical probe could be placed!

Already great in the lab it gets wonderful in the field.

The development system (PC based DSP and external i/o) is very different from the final system (embedded system with limited DSP resources). Porting is challenging and inefficient.

Algorithms development and testing with real world signals right from the design stage.

No surprises, from algorithms development to end product, the hardware remains the same. 

The C code generated for the target is hardly reusable. Each project leads to new coding and new debugging issues.

Software reuse (develop your DSP blocks out of the DSP library, design you own blocks, build complicated systems)

A new project leads to a new hardware development. Each project leads to entire new development and new debugging issues.

Hardware reuse (develop a mother board for each application, keep the SICORE DSP engine)

Inefficient code generation leads to using bigger and more power consumming embedded processors/boards.

Super efficient use of the hardware ressources (no C compiler), enables high troughput with low power consumption hardware (SICORE).



Other advantages related to laboratory work:

FIBULA-SICORE can also be used as a remote high resolution multi-channel oscilloscope and spectral analyser thanks to the real-time SCOPE feature of FIBULA!

Build you own complex measurement and signal processing system in software inside the FIBULA environement.

> 4 analog / 24bit ADC inputs and multiple digital inputs, including IRQ (trigger), with a single SICORE module.



Other advantages with respect to audio:


The multichannel 24bit/192kHz input and output anlog and/or digital makes SICORE ready for high quality audio

The scalable architecture of the DSP (24bit path with up to 48bit precision) enables great optimization of precision and memory usage for a given throughput

The large on-chip single-cycle accessible RAM allows single chip solution

High resolution fixed point processing outperforms 32bit floating point. See Documents

All with a low power consumption (approx. 5 times inferior to some other OEM DSP boards of equal effective processing power)

SICORE is versatile:

> it is already an embedded end-product on its own. Place it in a box, add jacks and a battery and go!

> if the CODECs are not up to your needs, plug SICORE in your system and use it as a DSP engine.





Although C compilers perform well on general purpose processors (Von Neumann architecture, VLIW, CISC/RISC), it has to be noted that they produce inefficient code for the particular DSP case (Harvard architectures, pipeline, DMA). (see Documents).


Don't get it wrong, some DSP implementations may seem more powerful at first glance, but they are usually only 16bit resolution. Cut their performances by 2 at least to compare to SICORE. Other DSP chips highly rely on their pipelined architecture, thus announced peak performance (MMACS) may never be reached in real applications.

Some other DSP implementations may seem to have more precision at first glance, but it has to be noted that 32bit float means 24bit precision (and 8bit exponent). One word takes more memory for the same precision. Refer to  Documents for in depth information.




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