Hardware - SICORE  DSP OEM board


Preliminary information.


Connect SICORE to the PC and start developing on DSP in a minute! 


To support the FIBULA software we developed SICORE, a credit card size module based on a dual-core DSP and a high peformance multichannel 24bit codec. The SICORE module can be powered by the host PC (USB bus) during the development phase, no other component is needed to startup. Once programmed, either use SICORE as a standalone module (just add jacks and a battery) or integrate it in your system as an OEM module (big component). Two SICORE modules can be placed next to each other on a Eurocard board and there is still room for many other components.



DSP engine

Dual-core 24/48bit 56bit-MAC  400MMACS 1200MOPS peak

Core architecture

Harvard, 3 fields (Program, X data, Y data), linear/modulo addressing
Efficiency 2 multiply and accumulate operations per clock cycle, no latency*


8 DMA channels
Timers 2 triple timers (including PWM), 2 watch-dog timers
Inter-core communication IRQ (maskable or non-maskable), shared RAM, polling

Available RAM

744kB RAM (248K words), core's RAM is single cycle accessible

Available ROM

2 x 4Mbit serial EEPROM for code and parameters


24.576MHz ultralow jitter onboard oscillator or external clock

Serial port spec

Serial port enables asynchronous DSP operation relative to i/o stream

Analog input/output

4 inputs / 6 outputs up to 24bit up to 200ksps (0.775Vrms level)

SPDIF audio 

1 SPDIF input + 1 SPDIF output (3V3 level)

Digital input/output

6 channels of input and output via I2S or any other formats

Asynchronous sample rate converter

Hardware, onchip, available from both cores


Memory expansion port (SRAM, SDRAM) on board's side connector
Communication 2 SPI master or slave (1 used for FIBULA) and GPIOs

I/O levels

All pins are 3V3 (5V compliant inputs)


All IRQ pins of DSP are made available on the board's connectors

Power supply


Pads spacing

2.54mm (100mil) for easy prototyping and integration


With its dual-core architecture, high resolution fixed-point arithmetic and large single cycle accessible on-chip RAM, the DSP provides high precision signal processing while keeping power consumption very low. It is ideal for standalone and embedded applications, general signal processing and audio. 


Up to 4 x SICORE modules can be implemented in a system and interfaced with FIBULA, making a DSP farm of 8 DSP cores with 52 analog i/o and many digital i/o, all controllable from a single PC with only one connection during the development phase!



*Clean architecture, high parallelism, low power consumption: this means real EFFICIENCY


SICORE's DSP provides a 24bit data path.

For audio purposes, it is the standard wordlength. It has to be noted that audio ADC/DACs rarely show more than 120dB of dynamics. As 24bit digital means 144dB of dynamics, the headroom is sufficient is most cases. When high dynamics is necessary, internal 48bit double precision can be used for either data or coefficients, or both. For fast industrial ADC/DAC of 10 to 16bits the headroom is huge. 


SICORE's DSP features absolute efficiency (see Documents and Q&A). 

The DSP performs 1 multiply and accumulate (MAC) in only 1 clock cycle and also prepares the data for the next MAC at the same time. The DSP's 3-field Harvard cores' architecture (program, data, coefficients) with optimized instruction set are ideal for efficient signal processing. Given that the DSP features two cores that can work in parallel and even asynchronously, throughput is assured, effortless, with low power consumption.


SICORE's DSP features great precision MACs along with low power consumption.

While IEE754 floating point multiplies can lead to rounding errors (32bit floating point is only 24bit precision and 8bit exponent), the fixed point 56bit accumulators of SICORE's DSP provide a great precision headroom. Such a precision can only be rivaled with floating point using double precision (64bits). But in that case, processing overhead can be more than x4 on floating point DSP chips, with a power consumption that can be well over x5. (see Documents and Q&A for details)


SICORE's DSP features a large and fast on-chip RAM.

The internal RAM is large enough for common signal processing tasks and a great portion of it is single cycle accessible! Other DSP chips require additional external RAM, which leads to wait states in communication with the core, with possible processing slow down.


SICORES' DSP is multi-core.

Each core can communicate with each other. Each core has its own i/o ports. Each core has its own local memory and also can share the common memory space. Applications are numerous: decoding in one core and coding in the other, etc.


MIPS, MFLOPS are not the only parameters to look for!




These are also the key arguments of NXP's CoolFlux DSP



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